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Espressif Systems /ESP32-H2 /I2C0 /SCL_SP_CONF

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Interpret as SCL_SP_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SCL_RST_SLV_EN)SCL_RST_SLV_EN 0SCL_RST_SLV_NUM 0 (SCL_PD_EN)SCL_PD_EN 0 (SDA_PD_EN)SDA_PD_EN

Description

Power configuration register

Fields

SCL_RST_SLV_EN

When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].
SCL_RST_SLV_NUM

Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.
SCL_PD_EN

The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
SDA_PD_EN

The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data